Abstract
In this thesis, we will present an e®ective thermal-aware chip stacking planner and a leadframe router to reduce the number of wiring layers in SiP designs. Our algorithm is conducted in two stages. In the ‾rst stage, we place each of bare dies to a feasible location and make sure that they do not violate the design rule and thermal constraints. In the second stage, we route the interconnection of stacked dies so that the routing resource is minimized.