Abstract
In this thesis, we describe a method of instruction scheduling and operand placement for complex processor architectures. Such processors possess irregular datapaths, multiple register banks, and incomplete internal connection networks, hindering the abilities of classical compilation techniques in generating efficient code. We discuss a port of the Open Research Compiler (ORC) to such a complex processor, a new VLIW DSP, called the Parallel Architecture Core (PAC). We examine PAC, observe and characterize the machine models of such architectures, and how they are different from contemporary processors. We find that for such architectures, the restrictions on operand transport, represents a new class of machine resource models. Such resource models are due to incomplete interconnection networks in the design, making structural properties emerge in such processors. Using the PAC processor as an example, we describe a machine learning method that formulates the problem state space as a storage mapping of data operands, and generate code for the PAC by doing combined instruction scheduling and operand storage assignment. We evaluate our algorithm using a benchmark suite for DSP processors, and find our technique to obtain approximately 35% to 40% improvement over a prior simplistic algorithm.