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Compilers for Configurable DSP Processors
Thesis

Compilers for Configurable DSP Processors

Chung-Ju Wu
Masters, 國立清華大學, 資訊工程學系
2002

Abstract

編譯器系統 目的機器描述機制 編譯器移植 暫存器轉換與傳輸語言 數位訊號處理器架構 Compiler System Machine Description Compiler Porting Register Transfer Language DSP Processors Architecture
DSP processors play an important role in present days. With different purpose, many IC-design houses could extend DSP architectures based on existing DSP processors. However, those architecture extensions may influence a lot on compiler design. In this thesis, we introduce the compiler model for portability and the interaction between architecture and compiler. We also propose the solution to solve the possible issues. Analyzing several DSP architectures, we found that some extensions would carry much impact on compiler. It causes serious problems so that we cannot do the porting easily. We use GNU GCC code generation as an example scenario. The solution to the problem is to focus on both hardware and software design. On hardware aspect, we have to change the design of the architectures in order to coordinate with programming model. On software aspect, it should deal with both front-end and back-end of the compiler. Front-end controls the RTL-generation rule and the only way to change it is to modify source codes. Besides, Machine Description is the back-end which controls the RTL-transformation rule. We have to change the components inside the Machine Description and add extra macros to support instruction expansion when needed. With the experiment, we assume that there is a new architecture derived from ADSP 2181. Then we try to migrate compilers for the derived architecture. In the process of migration, we experience the situation we mentioned above. We apply our solution to build a particular DSP compiler. Finally, we gather experiments and several statistics from GCC test patterns and benchmarks by using this new DSP compiler. This study will allow architecture designers to realize the impact they will make on compilers for the extension to their architectures.

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