Abstract
Recently, NAND flash memory has become a widely used data storage media. However, it has the endurance problem that each NAND flash block has limited erase cycles. Erase failure usually first occurs over 10K-100K erase cycles. This is inherent endurance characteristic of NAND flash, and in multi-level cell (MLC) NAND flash, this problem is more serious. Wear-leveling is a technique that distributes erase operations evenly to all blocks to extend the lifetime of a flash memory. NAND flash-based solid-state drive (NSSD) is composed of several NAND flash memory chips. To improve the performance, some multi-channel NSSD controllers have been proposed. These channels can operate parallelly and control different chips. In this thesis, a conditional threshold wear-leveling algorithm fitting multi-channel architectur is proposed. The overall wear-leveling operation is separated into several suboperations, and these sub-operations are distributed to different channels. This reduces the runtime of the wear-leveling operation. The conditional threshold value decreases when the average erase cycle increases. This can reduce extra erase operations cause by wear-leveling when the flash memory is young. As the flash memory becomes older, the smaller threshold makes wear-leveling work more frequently to get better performance.