Abstract
Timing estimation plays an important role in designing today`s microprocessors. To exploit the huge design space of processors, timing estimation must be performed very fast while maintaining sufficient accuracy. Cycle-accurate simulators such as Gem5 can produce very accurate timing information but are too slow. A viable alternative is to use functional simulators/emulators coupled with appropriate timing models. The problem is how to integrate the timing data from the timing models of different processor components, e.g. pipeline, branch predictor, and cache, to produce accurate timing estimation. On the one hand, as the processor components interact with each other in real machines, the timing models should also interact for accurate timing estimation. On the other hand, we hope that the timing models of different processor components be as independent as possible so that the models can be pluggable for configurability and their timing data can be reused for fast simulation. In this thesis, we present a configurable fast cycle-approximate timing estimation method for instruction-level emulators that addresses the above issue. We extend QEMU, a dynamic binary translation functional emulator, to allow timing models of different processor components to be plugged in to provide cycle-approximate timing information, while at the same time keeps the simulation speed fast by providing a Timing Record Caching technique. The latter requires that the pipeline timing of each basic block to be fixed and independent of other models. We show how this can done while still maintain timing accuracy. Finally, our tool also provides instrumentation and profiling capability to help designers analyze and find design bottlenecks.