Abstract
With the rapidly progress of VLSI technology, the complexity of a chip critically increases and the enormously growth of wires and gates, it becomes difficult to place buffers and route wires to meet timing in a limited space. In addition, it becomes necessary to consider congestion management intelligently while we insert buffers and route wires automatically. In this thesis, our contribution is to propose a new algorithm called CABIR to reduce the routing congestion cost by re-routing the initial Steiner tree and to generate some buffer candidate locations with the lowest total placement congestion cost. Then we pass the low congestion routing tree along with a set of low density buffer candidate locations as the input of the van Ginneken’s algorithm. Compare with the PRAB algorithm [13], the experimental results show that our approach is able to reduce timing, routing congestion cost and placement congestion cost up to 2%, 4% and 28% respectively. Also our runtime is fast.