Abstract
Memory system’s performance is still a significant bottleneck in today’s computer system due to the memory wall issue. In order to reduce the power and latency, DRAM vendors also hope that they can keep the characteristic of low production cost at the same time. Therefore, a new type of DRAM with asymmetric bitlines, called Tiered Latency DRAM (TL-DRAM), was put forward recently. Our target DRAM is similar to TL-DRAM, but we operate the small array like a cache, so we rename the DRAM as the Built-in Cache DRAM (BC-DRAM). In this work we propose a controller design with appropriate algorithms to get the most out of the BC-DRAM. In the proposed DRAM controller design, the data should be accessed from the small array as often as possible. If the small array does not contain the requested data, the requested data should be migrated from the large array to the small array. When the cache for small array is full and a new row address is requested to store in the cache, we need to determine the victim to be replaced. In this thesis, three replacement policies are integrated in the controller design to determine the victim, i.e., first-in-first-out (FIFO), least-used-first-out (LUFO), and earliest-used-first-out (EULO). We have modified the DRAMSim2, a cycle accurate memory system simulator, to test the algorithms of our controller together with a DRAM model. Based on the Wide-IO 3D DRAM specifications, our experimental results show that BC-DRAM with the proposed controller will consume lower power and achieve lower latency than the typical DRAM. Experiments are also done to show the effects of different specifications, such as sizes of small and large arrays, address scrambling rules, and number of ways of set association.