Abstract
Crosstalk comes from coupling capacitance between parallel wires, and is getting more and more important as technologies continue to shrink. According to simulation result, eliminating all crosstalk in 10nm technology can bring delay reduction ranging from 22.62% to 83.47%. Many researches have been published to alleviate crosstalk. However, some of them, like shield insertion and encoder/decoder, incur extra hardware overhead, and others focusing on low power do not handle crosstalk. In this thesis, we propose an innovative algorithm of operation and functional codes assignment to minimize crosstalk and reduce dynamic power on instruction buses. Our algorithm °ow includes target benchmark pro‾ling, adjacency and resource graph generation, clique partition, and code assignment. Experimental results show that our algorithm can decrease 4C crosstalk from 32.70% to 67.10%, 3C crosstalk from 21.93% to 36.32%, and bit transitions from 4.63% to 6.69%, respectively.