Abstract
3D integration is one of the promising technology to alleviate interconnection delay. Implementing 3D IC is to integrate 2D ICs with through-silicon vias (TSVs). For yield consideration, TSVs are bundled together as a TSV block. Regrettably, this placement results in crosstalk coupling noise in TSV block which may cause significant timing degradation. Traditionally, buffer sizing is one of the effective methods to solve the problem of timing. However, we observe that the increase of buffer size of aggressor TSV will cause more serious timing degradation to victim TSV in 3D than wires in 2D case. In this paper, we develop a delay model of a victim TSV surrounded by aggressor TSVs with different size of driving buffers. Based on the TSV delay model, we propose an ILP based buffer insertion method after floorplan stage. Our experimental results show that our proposed method can reduce 6.66% buffer area in average under timing constraint after floorplan stage as compared with a greedy method.