Abstract
On-chip interconnect has become the performance bottleneck as the number of cores and modules in a chip are increasing, particularly in data-intensive applications. In the modern System-on-Chip (SoC), the Network-on-Chip (NoC) is used to solve this problem. Several commercial approaches such as Alteris FlexNoC provides on-chip networks constructed from primitive building blocks, based on packet-based communication protocol. The interconnect design has a significant impact on the performance, area, and power consumption. Recently, many Electronic System-Level (ESL) timing models have been proposed to explore the design space with the constrained time-to-market. The accuracy and simulation speed are the trade-off in ESL simulation. In this thesis, we extend the concept of flit propagation model and present a timing model of flit transactions for primitive components in irregular packet-based interconnect fabrics. Based on the model, we then develop a fast timing simulator for on-chip interconnects with a 100\% cycle accuracy when validated with an industrial RTL implementation. We also propose a design space exploration flow to generate a partial-crossbar-based interconnect from the connection graph. With our timing simulator, we can evaluate and optimize the architectures of interconnects by adjusting topologies, FIFOs, outstanding buffers, data widths, and clocking. In a case of high-performance networking SoC, the proposed approach can explore the design space effectively, minimizing the latency of intercommunication to 43.6\% as compared with the initial architecture. The area cost can also be reduced to 88.1\% at the same time. With the different bandwidth requirement, the interconnect architecture can be optimized accordingly. The exploration result shows the trade-off between performance and area can be made easily with our timing model of on-chip-interconnect.