Abstract
Domino logic is one of the most popular dynamic circuit configurations for implementing high-performance and small-area logic designs. Since domino logic is inherently non-inverting, it presents a fundamental constraint of implementing logic functions without any intermediate inversions. Removal of inter-mediate inverters requires logic duplication for generating both the negative and positive signal phases, which results in significant area overhead. Therefore, it is important topic to minimize logic duplication for making a circuit inverter-free. In previous work, it is simply duplicating all the multi-fanouts nets on the way of pushing all the inverters to the primary inputs by De Morgan’s law called non-optimized logic duplication. Then, Ruchir Puri proposed the area overhead can be substantially reduced by selecting an optimal output phase assignment. In this paper, we present a previously unaddressed cycle-based logic optimization for minimum area duplication in dynamic logic synthesis. We formulated this problem as finding all the simple cycles with odd inverters in an undirected graph and then there is a constraint formula is made for representing these cycles. Satisfying this formula could be taken as an unate weighted covering problem. In addition, this paper also presents a heuristic algorithm for solving the unate boolean constraint formula. Our experiment results show that in average there is about 14% improvement from the non-optimized logic duplication; moreover, they are also better than the results using the output phase assignment.