Abstract
With the increase of need for high-function electronic devices such as DRAM chip, electronic devices are being pushed towards high density, lightweight and miniaturization. To attain the goal, a fine circuit rule and high speed device are generally required. As the line space and width of IC interconnect continue decreasing, the parasitic capacitance and resistance of devices would correspondingly increase and, unfortunately, result in the increase of RC delay. It can be however improved by using copper (Cu) metallization and low dielectric materials. However, in spite of the advantages of enhancing electrical performance, the Cu/Low-k layer results in softer mechanical response and weaker adhesion. This can cause interfacial delamination in the interconnect structure of DRAM chip. These problems of DRAM chip in this research work worth further study. This work mainly discusses thermal-mechanical analysis of metal/dielectric pad structure in DRAM chip in the process of wire bonding and thermal cycling test with ANSYS® program. Firstly, the three-dimensional global-local finite element method is used to analyze metal/dielectric pad structure offered by X company, and to evaluate the effect of different low-k materials on stress in Cu/Low-k interconnect and different metal/dielectric layer thickness. Secondly, according to different layout design of via array structures, analyze how to improve the pad reliability in the process of wire bonding, and further analyze what the width of via array structure has influence on structure stress. According to the results, the metal/dielectric pad structure in DRAM chip offered by X company does not have any thermal-mechanical trouble in the process of thermal cycling test and wire bonding. In Cu/Low-k interconnection, FSG is the better Low-k material to choose. Through parametric analysis, increasing C2 layer thickness contributes to decrease stress of via structure in the process of thermal cycling test. Increasing C2 and M2 layer thickness also contributes to decrease stress of via structure in the process of wire bonding. Based on the analysis of layout design of via array structures, “plug-chessboard” via array structure is the better one to choose. Through parametric analysis of “plug-chessboard” via array structure, it is helpful to decrease stress when the width of metal material of C2 layer is 0.5 times of M1 layer, or metal material of C1 layer is 0.5 ~ 0.75 times of M1 layer. The results achieved in this work can not only help us to understand the thermal-mechanical behavior of metal/dielectric pad structure in DRAM chip during thermal cycling test and wire bonding process, but also offer an initial design stage for electronic packaging industry.