Abstract
In this thesis, we present the efficient debug and trace technology for the embedded DSP core, which can facilitate the software/hardware co-development and co-verification of the DSP platform. With the previous constructed DSP platform called Starfish, a test chip and its prototype are implemented for the demonstration. By evaluating the DSPStone benchmarks and some realistic multimedia applications such as H.264 and MP3 decodings, we propose several compression approaches for tracing the content of the program counter and register file. The compression technique compacts both the spacial and temporal information when taking advantage of the practical properties of the processor. The compression rate of the program counter can achieve 87.57% on average; while the compression rate of the register file is 98.5% as compared with the original raw data. In addition, the debug and trace design is also implemented, which improves the trace efficiency as compared with the previous work. The forward and backward trace capability is also considered in our architecture, making the design practical for both the pre-silicon validation and post-silicon verification. The architecture can also be extended to process the real-time tracing if the pipeline scheme is affordable. Our future works include the further improvement of the compression rate of the traced data; the support of monitoring the data transactions of the cache and on-chip bus; and the debug and trace of the multi-core system.