Abstract
Low-density parity-check (LDPC) codes have been demonstrated to achieve near-capacity performance with iterative message-passing decoding and sufficiently long code length. Therefore, LDPC codes have attracted considerable attention because of their outstanding performance. Quasi-cyclic LDPC (QC-LDPC) codes with structured parity-check matrices are one type of LDPC codes. The advantages of QC-LDPC codes are efficient encoding/decoding and reduced complexity of very-large-scale integration (VLSI) implementation. Traditional QC-LDPC codes provide equal error protection in the whole codeword; that is, each codeword bit exhibits the same performance regardless of its importance. QC-LDPC codes with unequal error protection (UEP) properties have different error-correcting capabilities for different parts of the codeword bits. The more important bits can have more protection. LDPC decoding is usually executed by using iterative message-passing decoding based on the sum-product algorithm (SPA). However, conventional decoding algorithms were not designed for LDPC codes with UEP properties. In this thesis, we propose three decoding scheduling schemes for UEP QC-LDPC codes based on existing scheduling strategies. Simulation results are presented to verify that the proposed schemes can provide better bit error rate (BER)/block error rate (BLER) performance for a fixed number of iterations for subcodewords that are not on the higher protection levels. Furthermore, the average number of iterations can be reduced, thereby reducing the decoding computation complexity.