Abstract
As the semiconductor fabrication technology continues to advance and device feature size and supply voltage are being scaled down following Moore’s Law, it is getting harder and harder to tackle with all kinds of variation and uncertainty. As a result, the number of undetected defects that are contained in shipped products using advanced technologies rises rapidly, driving their Defect Level (DL) up. Those defects apparently are not covered by conventional Stuck-At Fault (SAF) and Transition Fault (TF) models, which are typically used by commercial products to guarantee the product quality before shipping. A high DL means that a high number of defective devices pass the final test and are shipped to the customer, which will eventually cause escalating overhead (extra cost) due to unacceptable system product quality. In order to reduce the DL, there are many methodologies proposed recently. The Cell-Aware Test (CAT) methodology was proposed to target the cell-internal open and short defects which are more realistic than the conventional gate-level test flow. However, so far it has not been well proved that CAT can reduce DL effectively and efficiently for most advanced products, i.e., higher defect coverage is still of high priority in the agenda. Another issue is that the original CAT approach is very time-consuming. This issue has been addressed recently by one of our group members, Hsuan-Wei Liu, who has proposed a novel layout-based method to reduce the defect set by removing redundant or unnecessary defects [5]. In this work, we stress the issue of improving the defect coverage. To demonstrate our approach, we simulated 32 standard cells from a typical commercial 180nm CMOS cell library, for both the open and short defects. The defect set that we use is from the enhanced CAT method based on cell layout [5]. By SPICE simulation for each and every defect in the set, we obtain the extra information for the leakage current, so we are able to identify those defects that cannot be detected by the voltage (logic) test in the original CAT approach. Note that the layout-based CAT has a comparable defect coverage with the original CAT, so in our work we compare the defect coverage at the cell level between the layout-based CAT method [5] and the proposed leakage-current enhanced CAT, with a commercial ATPG tool. The layout-based CAT with SAF and TF tests can detect 93% of the open and short defects as defined in the reduced defect set. With the leakage-current enhanced CAT, the defect coverage can increase by 7% on average, and reach 100% in all cases (for all cells). Finally, we also calculate the defect coverage by the SAF and TF patterns, respectively, with a commercial ATPG tool for the layout-based CAT [5]. The defect coverage by the SAF patterns is 89% on average, i.e., about 11% of the defects cannot be covered by the SAF patterns. We then calculate the extra defect coverage that can be achieved by the TF patterns, which is 4%, so the total defect coverage is 93% on average as mentioned above.