Abstract
FinFET is a solution to the process-scaling problems, such as short channel effect and large leakage. The thin body of FinFET is typically lightly doped, thereby eliminating the threshold voltage deviation caused by random dopant fluctuation effects. The FinFET-based SRAM, therefore, has high stability and low power consumption. However, FinFET has its specific defect models due to the special fin structure. The defects occurred on nanowire could affect fins of multiple transistors according to FinFET-specific layouts. Targeting these defects, we propose some criteria to investigate defect candidates from schematics, then simulating and summarizing the corresponding fault models. In our summary, there are special defects, vague defects, causing no logical fault but leading to reliability degradation, especially in deep sub-micron technology. Focusing on vague defects, we further propose a method to test them. In order to improve defect level, we propose a testing strategy that achieves high diagnosis resolution to identify these defect candidates with read current sensor support. A defect dictionary is finally built by this method, assisting in fast defect diagnosis for the FinFET-based SRAM in the future. In this thesis, we inject these defects respectively to each transistor in FinFET-based 6T-SRAM circuits for simulation. The testing strategy has been validated by SPICE simulation using 20 nm low-standby power (LSTP) model cards from the PTM website (Predictive Technology Model).