Abstract
Factors of delay variation such as process variation and noise effects may cause a manufactured chip to violate the pre-specified timing constraint. Traditional methods add a pessimistic timing margin to alleviate delay variation problems. In this thesis, we propose a re-synthesis technique to tolerate delay variation for domino circuits. Note that slacks of nodes along critical paths is zero; any delay addition to those zero-slack nodes will worsen the final performance of a circuit. Our basic idea is to increase slacks of nodes in the critical region by appending a redundant auxiliary sub-circuit to the original circuit. The auxiliary sub-circuit can cause critical paths to become false paths or imperceptible paths [8] so as to improve the capability of delay variation tolerance. Experimental results are very encouraging.