Abstract
The channel model of 802.16 used by the 802.16 group is the SUI model (Stanford University Interim) with modified path loss model (from Hata’s model). In the thesis, a channel emulator for 802.16 is investigated and implemented. The channel effects are divided into three parts: 1. Microscopic effects (SUI model) 2. Macroscopic effects: Path loss and shadowing, AWGN 3. System error: frequency offset, I/Q imbalance and clock error Firstly, each part is briefly explained and combined to construct a GUI-based software channel simulator to support simulation of the effects of single channel parameter or combination of parameters. Different hardware implementation structures with different working frequency, chip area and numbers of adders/multipliers are then studied and a structure that can support fast throughput at the limitation of chip area is proposed for implementing the channel emulator on the FPGA chip. The Xilinx XC2V4000 FPGA chip is used as the platform in our implementation. Simulations and experiments are also performed to verify the implemented channel emulator.