Abstract
As the CMOS technology coming to nanometer scale, process variation increasingly deteriorates the yield of mass production. Here we propose to employ a row-based tunable design methodology which allows users to adjust the supply voltage, as well as the body bias. The method presented in this thesis is able to mitigate the effect of process variation by fine-tuning the supply voltages for fabricated chips that fail the expected specification. In our method, the voltage difference between rows is small enough so that the level conversion is not required between lower supply voltage cells and higher ones. In order to facilitate design process and reduce designers' efforts, we automate the process of modifying designs at the auto-placement-and-route (APR) stage. The modified flow is completely compatible to the currently adopted cell-based design flow. In the experiments, we have applied our method on 180nm process node, and constructed a prototype of the tunable circuit. Then, the area estimation shows that the area overhead of the tunable components is less than 5%. Even including the power gating circuits, the total area overhead is just about 10% in large benchmarks. In all configurations of supply voltages and body biases, the best leakage and dynamic power savings of the tunable s9234 benchmark are 98% and 22%, respectively. Moreover, the path delays is reduced by 19% on average, and the deviation of path delay distribution tightened 20% for the best case.