Abstract
Creating a new FPGA is a challenging task. Currently it takes approximately 50 to 200 person years from architecture exploration, CAD tools development, circuit design, layout to verification [1]. Our work focused on hardware implementation of the FPGA with a new developed hierarchical connection topology(HFPGA), since the development of the CAD tools for this connection topology has been addressed in [2, 3]. We proposed a methodology to shorten the design time of the HFPGA by adopting the regularity we explored to automate the process of the complicated interconnection routing. A case of a four level HFPGA layout was constructed. Simulation result reveals the circuits implemented in the HFPGA functioned correctly. In addition, we modified and improved the interconnection delay BIST circuit [4] for our HFPGA. Simulation results indicated that the delay testing techniques can be applied to the HFPGA successfully.