Abstract
Power or energy has become one of the most urgent issues in VLSI designs in recent years. Dynamic power management (DPM) can alter the power level of the system/components during the runtime, preventing from the overheating of the circuit, and also prolonging the battery life for portable systems. However, the non-stationary characteristic of the workload, which is usually not predictable in the design phase, makes the DPM patterns and applications dependent by nature. Traditional DPM relies on complicated statistics and probability models, which are suitable only for high-level software implementation. In this thesis, an approach for the power-adaptive design methodology is presented. Our power adaptive system consists of behavior-level and RTL components. The host, dynamic power manager, clock generator, and the voltage regulator with realistic parameters are mod- eled in SystemC, whereas the AHB bus wrapper and the target example, AES crypto-engine with asynchronous interface, are the RTL designs. In addition, the non-stationary requests are modeled as a stochastic Poisson process. And the proposed power manager features a workload-driven policy to monitor the incoming AES requests. Considering the realistic characteristics of clock generator and voltage regulator when changing the frequency and power, the performance and energy trade-o® can be explored and evaluated by using our system-level simulation environment. The experiment results show that our power adap- tive approach can provide high energy e±ciency and about 52% energy saving on average. The architecture is simple and e®ective for the hardware implementation. Our approach can be easily adopted for other data-intensive processing elements such as cryptographic accelerators, digital signal processing units, and communication modules, etc.