Abstract
The proposed load-balanced Birkhoff-von Neumann switch can achieve ultra high speed switch capability with N × N TDM switch via recursive construction. In this thesis, three architectures were implemented. The first one was an 8 × 8 TDM switch with serial input/output ports and embedded 8/10B CODEC for Ethernet applications. The second one was an 8 × 8 TDM switch with parallel input/output ports and embedded 8/10B CODEC using high speed interface. Another modified architecture is also included. The last was a dual-mode parallel 8 × 8 or serial 64 × 64 TDM switch for high speed networking application. A novel testing circuit was also implemented to easily verify switching results. All implementation were based on the 0.18 µm CMOS technology.