Abstract
Because of the memory access time limitation on switching speed, the input buffered crossbar switch architecture has been widely used for high speed networks. However, the potential Head-Of-Line blocking may reduce the throughput. In order to provide service guarantees, various scheduling algorithms with special Virtual Output queueing technique have been proposed to overcome this problem. The Birkhoff-von Neumann crossbar switch has been shown to provide uniform service guarantee for all non-uniform traffic and achieve 100% throughput without framing or internal speedup. In this thesis, we design and implement an 4×4 input-buffered Birkhoff-von Neumann crossbar switch by carrying out its on-line algorithm and switching fabric on a FPGA chip.