Abstract
The high data rate and the quality of transmission is attached great importance in recent years.Though the multiple-input-multiple-output (MIMO) system can achieve these requirement, the new MIMO technology called generalized spatial modulation MIMO (GSM-MIMO) that has additional consideration about power consumption.This thesis proposes a hardware design of CECML-OB-MMSE detector \cite{CECML} called parallel 4 shared index processing with joint QR-SIC in GSM-MIMO system.At the index selection, the new algorithm uses shared index method instead of memory access to reduce hardware resource and computational complexity.And the parallel technology trades off the hardware latency and area.At the symbol detection, we use joint QR-SIC detector \cite{JQRSIC} instead of MMSE detector to avoid matrix inverse and decrease hardware latency.After using error correction code (ECC), the BER performance of this algorithm is close to maximum likelihood (ML).The hardware architecture is designed and verificated by FPGA. The analysis of hareware area, hareware timing and hareware power are presented as well.