Abstract
HDR (High Dynamic Range) is a technology that can sample and restore the colors of our real world extremely loyally, but cannot be displayed or used on conventional devices without properly reproducing. As a result, there are several tone mapping methods proposed to transform HDR to common formats so that we could utilize HDR more widely. In this thesis, we design an integrated hardware architecture to perform two different real-time High Dynamic Range Compression methods (Gradient Domain Compression and Global Tone Mapping) in one chip. The speed of our chip is improved from 50 MHz to 100 MHz in TSMC .13 μm technology, and it has an area of 14.059 mm2 with consuming a power of 177.147 mW. In the meantime, the critical paths and internal architecture in those two designs are also improved and well-optimized.