Logo image
Design and Implementation of Low-Complexity Detector for Space-Time Permutation Modulation MIMO Systems
Thesis

Design and Implementation of Low-Complexity Detector for Space-Time Permutation Modulation MIMO Systems

Yeh, Yu Cheng
Masters, 國立清華大學, 電機工程學系
2016

Abstract

空時排列調變 空時排列碼 空間排列調變 多輸入多輸出系統 偵測器 球面偵測器 排序球面偵測器 多候選選擇匹配最高比結合偵測器 現場可程式化閘陣列 Space-Time Permutation Modulation Space-Time Permutation Code Spatial Permutation Modulation MIMO System Detector Sphere Detector Ordered Sphere Detector Multiple Candidate Selection Matched-MRC Detector FPGA
In the past few years, the number of mobile devices are more and more. Not only to the functions of the mobile devices, people attach great importance to the transmission quality as well. A new MIMO technology called Space-Time Permutation Modulation MIMO(STPM-MIMO) has additional consideration about transmission reliability. Based on the STPM-MIMO technology, this thesis proposes three detector algorithms, which are Sphere detector(SD), Ordered Sphere detector(OSD) and Multiple Candidate Selection Matched-MRC detector(MCSMMD) algorithms. SD and OSD algorithms are optimal detector algorithms, and their BER performances are the same as the benchmark, Maximum-Likelihood(ML) detector algorithm. The computing complexity of SD algorithm is about 15.6 percent of ML detector algorithm at high SNR. OSD algorithm can improve the efficiency of SD algorithm. The computing complexity of OSD algorithm is approximately 33 percent of SD algorithm at high SNR. Although SD and OSD algorithms have the ML performance, they are not suitable for hardware implementation. MCSMMD algorithm is sub-optimal detector algorithm; however, it is a easier and flexible hardware implementation detector algorithm. The computing complexity of MCSMMD algorithm is approximately 10 and 5 percent of OSD algorithm with very little performance loss at SNR 30 and 0 dB, respectively. In this thesis, two versions of hardware architecture of MCSMMD algorithm are proposed, implemented and verified by FPGA(xc7vx690t-3ffg1157). One version has higher throughput(539Mbps) but higher utilization; the other version has lower throughput(8.8Mbps) but lower utilization. The analysis of hardware timing and hardware area are also presented in the end.

Metrics

1 Record Views

Details

Logo image