Abstract
In coding theory, turbo codes have been the breakthrough in recent years. Among these, the maximum a posteriori (MAP) probability algorithm is a powerful soft-input soft-output (SISO) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This thesis presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Besides it adopted the concept of the border metrics to reduce the memory size and the power consumption of the memory accesses. Based on the scheduling analysis, the forward recursion can be reversed in order to be directly operated on with backward recursion. The comparison result shows it can effectively reduce the memory size up to more than half size of the previous works. In addition, we also simplify the memory data access without an extra address generator.