Abstract
In this thesis, standard specification study, functional simulation, architecture design, and circuit design along with chip implementation of an IEEE 802.15.4 baseband transceiver for low-rate wireless personal area network (LR-WPAN) with full digital synchronization is presented. In order to estimate and compensate carrier phase error at baseband, the receiver adopts full digital solution for carrier phase synchronization. An existing packet detection algorithm for spread spectrum communication systems is used for estimating quite large carrier frequency offset. A new decision-feedback algorithm to track residue phase error for long packet length is also proposed in this thesis. The proposed receiver achieves system performance (PER = 0.01) at SNR less than 5 dB. It provides better performance than the standard required. The baseband processor was implemented in simple hardware architecture and designed with low power techniques. Gated-clock is used for time scheduling to save power consumption. The transceiver chip is fabricated with TSMC 0.18 um 1P6M CMOS technology. The area is 1.633 mm X 1.633 mm, and the power consumption is about 4.7 mW at receiver mode.