Abstract
With the improvement of chip manufacture process, a single chip may contain more and more functional units. The chip design concepts have emphasized more on the co-operation of a single chip than the improvement of each functional unit. For these reasons, a high efficient interconnection is necessary. In the past few years, the most frequently used interconnection is global shared medium bus. However, the efficiency of this method is very poor and the deep sub-micron wiring effect is very severe. In order to improve the interconnection efficiency, pipelined bus and segmented bus were proposed. These methods can further improve the interconnection efficiency; however, their performances are severely limited by the bus centric feature. For these reasons, a network on chip (NoC) design concept was proposed. In this thesis, we are going to discuss the design of on chip interconnection network and their performance evaluation. First, we propose a new network buffer design concept, which eliminates the cycle delay due to state switching. By adopting this buffer architecture, we build up three different types of networks based on three different network topologies. These networks can support multiple data transfers simultaneously. We also optimize the network nodes in each network to further improve the network performance and reduce the extra cost on both hardware complexity and intra-node wirings. In addition, we propose a physical channel resource management scheme and prove that it is a good solution for multiple virtual channels to share one physical channel resource. After designing the networks, we build up a simulation environment based on SystemC, which can describe the detailed behavior of each network component in cycle accurate RTL level, and support fast network performance evaluations. Using this network simulation environment, we have done lots of network evaluations, which show the design tradeoffs between hardware cost and network performance in different situations. This information provides a guideline in NoC design, and is very useful for further performance improvements.