Abstract
Phase-locked loops are widely used in many applications for clock generation and synchronizations. The signal’s timing quality is of critical importance to the system’s performance. As more and more modules are integrated into the same chip in SoC era, the noise on the supply rails becomes larger and more significant. Many prior works have investigated the performance degradation due to supply noise and proposed techniques for improvement[4], [7], [8], [10]. In this work, we have designed and implemented a PLL using a CMOS ring oscillator for its wide tuning range from 200 MHz to 1.6 GHz. Furthermore, current-starved structure is used for delay cells for its rail-to-rail characteristics. However, ring oscillators are more susceptible to supply noise than the LC counterpart. In this design, the current mirror ratio is changed according to the operating frequency for optimal balance between the signal swing and charging current. This leads to low supply sensitivity over the tuning range. The measured supply sensitivity is from ?0.9%/% to 1%/% over the entire tuning range, and is close to zero for 500 MHz to 1.2 GHz. The peak-to-peak absolute jitter is measured to be less than 20% of the oscillation cycle with 10-mV supply noise at 20MHz, and the peak-to-peak cycle jitter is measured to be less than 4%. The entire PLL consumes 36.17 mW at 1.6 GHz.