Abstract
Due to ever increasing the advance of silicon technology, the complexity of System-on-a-Chip (SOC) design keeps growing rapidly as the number of cores increases. Many-core SoC with Network-on-Chip (NoC) is popular used in today. However, traditional verification and debugging approaches aim at individual cores or on-chip communication network, but the parallel application is also important on many-core systems. The verification of design and the debugging cooperating with parallel application and hardware with a lot of processor cores is the most of challenging tasks and has become extremely important for many-core systems. In the thesis, we present the architecture of the proposed embedded tracer on the proposed many core platform and methodology for application-level communication that focus on NoC's traffic situation and inter-core communication. We also improved several lacks on the previous tracer. For example, finding out the cause of packet congestion needs huge trace data, and previous communication event trace loses some information useful. The proposed communication tracer consist of trace configuration unit, communication trace unit, NoC switch trace unit and trace bus system. Trace configuration Unit provides to configure tracer at run-time. Communication trace unit monitors the communication event on each PEs' communication unit. NoC switch trace unit is used to monitor transaction on the NoC which users may be interested in. Trace bus system is used to packet trace data from communication trace unit and NoC switch trace unit, and store them to embedded trace buffer. The case study shows that the proposed communication tracer can effectively collect information form the communication unit and the NoC to inter-PE communication performance analysis and debug. Experiment result shows that the reduction ratio of NoC trace data in our proposed communication tracer can achieve between 87.96% to 99.98% depended on various cases. By using our proposed time high offset method can reduce time beacon from 85.72% to 95.19%. In addition, the area of the proposed communication tracer cost is only 1% compared to the many-core platform without speed penalty.