Abstract
This thesis presents an integer-N phase-locked loop (PLL) for Ku-band low-noise block (LNB) downconverter in satellite communication systems along with two class-C voltage controlled oscillators (VCOs), two high resolution time-to-digital converters (TDCs) utilizing a novel calibration-free time amplifier, and an active programmable time shifter for 5.8 GHz full-duplex radio analog echo cancellation (AEC) circuit. All the presented circuits are fabricated in TSMC 90nm CMOS process. The first class-C VCO is designed with push-pull topology with a transformer biasing technique. Fabricated in TSMC 90nm CMOS process, the VCO achieves a phase noise of -121 dBc/Hz at 1MHz offset with an FoM up to 190 dBc/Hz. The second class-C VCO which is used in the PLL follows the conventional topology, and a digital-controlled capacitor bank is added to widen the frequency tuning range. The PLL is designed to cover four frequencies for both DVB-S and ABS-S standards, including 9.75 GHz, 10.6 GHz, 10.75 GHz, and 11.3 GHz. Using the second class-C VCO with digital band control, the PLL can be successfully locked in these four frequencies. We also propose a novel calibration-free time amplifier for high resolution TDCs, which is the most critical block in multi-step TDC topologies. With the time amplifier, the designed 9-bit four-stage TDC has achieved a desired time resolution of 0.86 ps in measurements, but the linearity is not as good as the simulated results due to offsets. In the second TDC design, the popular 1.5-bit cyclic structure is introduced to improve robustness of the TDC. The proposed 9-bit cyclic TDC has the advantage of area reduction with a similar simulated resolution of 0.86ps. Although the circuit is still under fabrication, we expect the measured results will be closer to simulation compared with the previous design. The last circuit introduced in this thesis is a programmable active time shifter, which uses the gm-C all-pass filter to approximate a true time delay transfer function. The proposed structure consists five digital control bits with a group delay step about 10 ps, which can cover the desired time step for 5.8 GHz AEC circuit. The group delay ranges from 100 ps to 370 ps at 5.8 GHz, and the maximum group delay discrepancy over a GHz bandwidth is only about 10 ps, which shows a sufficient flatness.