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Design of Millimeter Wave PLL Building Blocks and Transceiver Front-ends
Thesis

Design of Millimeter Wave PLL Building Blocks and Transceiver Front-ends

Lo, An-Hsun
Masters, 國立清華大學, 電子工程研究所
2013

Abstract

毫米波 除頻器 壓控振盪器 收發機 millimeter wave frequency divider voltage-controlled oscillator transceiver
With the coming of the era of high-speed data, wireless communication systems must operate at increased frequency bands to transmit such explosively growing data. The millimeter wave frequency range (30~300 GHz) has a sufficient bandwidth which is very suitable for GHz and tens-of-Gbps applications. In this thesis, we mainly focus on realizing building blocks for phase-locked loop and transceiver front-end in V-band (57~64 GHz) and W-band (75~110 GHz) with CMOS technology. In V-band, we have introduced a reference-less optical-RF interface transmitter (TX) in TSMC 90-nm CMOS technology. We propose “carrier recovery” technique to extract the clock of data directly. The signal is then multiplied to 60 GHz for system integration. Therefore, in real applications, there is no need for using a crystal oscillator as the reference clock, and the system can still transmit the data. The tuning-range of the proposed carrier is about 5 GHz and the phase noise is about -87 dBc/Hz at 1-MHz offset. The TX provides a maximum output power of 5 dBm with a bandwidth of 14 GHz. The maximum transmitted data rate is 2.5 Gb/s with BPSK modulation. The total power consumption of the system is 256 mW with a 1.2 V supply voltage. We have also realized a 79 GHz voltage-controlled oscillator (VCO), an 80 GHz OOK demodulation receiver (RX), and a 105 GHz frequency divider in TSMC 90-nm CMOS technology, all in the range of W-band. For the 79 GHz VCO, we introduce a “trifilar tuning” technique to overcome the poor quality factor of the varactors at high frequencies. Besides, we combine another technique called “double-stacked cross-coupled pair” to enhance the negative resistance of tank at high frequencies in order to ensure oscillation. The VCO provides about 5.6 GHz tuning-range with a phase noise of -107.7 dBc/Hz at 10 MHz offset. The core power consumption is about 7.3~25.6 mW with a 1.2 V supply voltage. For the 80 GHz OOK demodulation RX, we improve the insufficient bandwidth of the conventional envelope detector, and propose a Cherry-Hooper based envelope detector with inductive peaking to enhance the operation bandwidth. We have realized an envelope detector operating at 12.5 Gb/s, at central frequency of 80 GHz. The IP1dB of the RX is about -16 dBm. The output peak-to-peak jitter is about 8.7% UI. The total power consumption of the system is 67.5 mW with a 1.2 V supply voltage. For the 105 GHz frequency divider, a divide-by-5 injection-locked frequency divider (ILFD) with a transformer tank was proposed to reduce the effective capacitive loading from the output buffers. Moreover, another inductor is added to resonate with the parasitic capacitances of the injectors and solves the problem of insufficient gain. The divider provides about 4 GHz locking-range at central frequency of 105 GHz. The core power consumption is about 5.7 mW with a 1 V supply voltage.

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