Abstract
Low-density parity-check codes were first introduced by Robert Gallager in the early 60’s. They are linear block codes which have sparse parity check matrices and provide performance that comes quite close to the Shannon limit. With the advanced technology, implementing LDPC code decoder is not an impossible thing and there are more and more researches on LDPC codes. There are also many communication systems adopt LDPC codes as their channel coding, such as 802.11n and 802.16e. Although LDPC codes have excellent decoding performance, realizing it is never an easy job. There still exist many challenges when implementing LDPC code decoder. The high routing complexity, large chip area and high power consumption all need to take into concerns. In this thesis, we present architecture design, functional simulations and the comparison of decoding performance using different decoding algorithms for IEEE 802.16e LDPC decoder. We will find that there is a trade off between error-correction capability and hardware complexity. The most suitable decoding algorithm “Layered Belief Propagation Algorithm” with min-sum is chosen to implement. The proposed LDPC decoder is implemented by SystemC to do the data flow simulation and use Synopsys Design Compiler to help us to find the critical path. The timing information of Design Complier is then used to estimate the throughput. We use three design techniques in our LDPC decoder: 1. Reconfigurable architecture for all kinds of code rates in 802.16e, 2. Use Benes network to solve routing problem between bit nodes and check nodes, 3. Reorder the model matrix when choosing specific code rates.