Abstract
With the data volume of transmission and processing getting larger and larger, in order to solve the non-ideal effects of conventional metal lines, more and more researches put efforts on optical interconnects. In this thesis, we focus on designing ultra-high speed front-end circuits of optical communications. The first three chapters show the design and implement of optical transceiver in standard CMOS technology. In chapter four, we use the SiGe HBT technology to achieve a faster receiver front-end circuit. Finally, a conclusion is given in chapter five. In chapter 2, a 40-Gb/s transimpedance amplifier with an inductor peaking technique in 90 nm CMOS has been implemented. The power consumption of the TIA without output buffer was about 10.5 mW under a supply voltage 1.5 V. The TIA reached a transimpedance gain of 52 dBΩ with an operation speed of 25 Gb/s. The chip area is 0.4*0.45 〖um〗^2 including four 3D solenoid inductors with a core area of only 0.024 〖mm〗^2. The measurement results show this design is suitable for 25 Gb/s operation. In chapter 3, a compact 40 Gb/s inductorless modulator driver is proposed and implemented in 40 nm CMOS for the purpose of integration with the silicon-based high speed modulator, provided by University of Southampton Optoelectronics Research Center. Under the termination of 50Ω, the modulator driver can reach 1.66 V_PP and 1.4 V_PP at the data speed of 12.5 Gb/s and 25 Gb/s. The power consumption is 337 mW under the supply voltage 2/4 V and the core area is only 0.012 〖mm〗^2. In chapter 4, a 100+ Gb/s inductorless transimpedance amplifier is proposed and implemented in 0.13-μm SiGe, provided by Innovations for High Performance Microelectronics (IHP). The simulated results show a 3-dB bandwidth can achieve 110 GHz while only consuming 22.8 mW under a supply voltage of 3.3 V. The transimpedance gain is 50 dBΩ and the chip area is 170*500 〖um〗^2 with the core area of only 30*50 〖um〗^2. The eye-diagram at the speed of 100 Gb/s shows well opened in the simulation results.