Abstract
With the rapid growth of the wireless communication market, mankind has entered the era of the high-speed data transmission. For so many wireless applications such as mobile phones and wireless local area network (WLAN), the CMOS integrated circuits with low cost and high integration level play an important role to improve the system performance, operating with increased speed, reduced power, and more complicated functions. However, scaling of device feature size is approaching the physical limitation, and the continuation of Moore’s Law becomes even questionable. A promising solution to this issue is the three-dimensional (3D) IC technology. By using the Through Silicon Vias (TSVs), the stacking dies can significantly shorten the interconnections in conventional 2D IC leading to reduced power consumption and increased operation speed. The local oscillator (LO), which converts either up or down the input frequency, is the heart of the phase-locked loop (PLL) in a frequency synthesizer. This thesis focuses on the related circuits in a PLL using both 2D and 3D IC technologies. First, the design of an ultra-low voltage VCO (voltage controlled oscillator) is presented in chapter II. By using the transformer feedback technique and adding the gate inductors, this circuit could operate at voltage less than 0.5 V and get the advantage of high tuning range at the same time. To the author’s best knowledge, the achieved tuning range is the highest compared to other reported low voltage VCOs. Second, after establishing the equivalent circuit models of the TSVs (Through Silicon Vias), we proposes a V-band VCO configuration making use of the TSVs in 3D IC technology as the inductor in the LC tank, as shown in chapter III. The VCO allows dual-band operation, and only takes a chip area about 1/10 of the traditional 2D VCO. In chapter IV, a U-band VCO (f0= 50 GHz) based on dual admittance transforming cross-coupled pair is presented in chapter IV, and the proposed VCO could operate at U band under very low power consumption (0.74 mW) even in 0.18 μm CMOS. A integer-N PLL is presented in chapter V. Operating at 5.12 GHz, the fundamental frequency provided by the VCO is divided by the divider using current mode logic (CML) and divider in true single phase clock (TSPC), and then feedback to the input to compare with the 20 MHz input frequency. The resulted phase difference then cause the charge pump to charge or discharge the capacitor. After filtering by the loop filter, the high frequency component is removed and the DC component is used as tuning voltage to change the frequency of VCO. Eventually it locks at the 5.12 GHz. The simulated results show that the pre-layout simulation is consistent with the theory and could be expected to be the basis and experience of the future design. Finally, chapter VI concludes this work and provides recommendation to the future work.