Abstract
Previously, a Network-on-Chip (NoC) based many-core platform has been proposed. This platform features a dedicated hardware module to support a message passing communication library for parallel programming. However, only blocking communication is supported in the previous platform. During blocking communication, the processor cores have to stop computation and wait in a busy loop to check communication status. It is possible that a long communication latency (including waiting time for network transfer and response at the other end) will lead to less efficient computation resource allocation. In this thesis, we proposed a communication unit which supports both blocking and non-blocking data transfer. Based on the hardware infrastructure, a set of non-blocking message passing application programming interface (API) is also developed for programmers to overlap computation and communication which may improve the overall program efficiency. We designed our communication unit and APIs with SystemC/TLM for an early stage evaluation and verification at both hardware and software levels. The experimental results show that the average ratios of computation cycles needed for non-blocking and blocking is 2 (burst mode) and 1.77 (single mode). In addition, we also used a high-level synthesis (HLS) tool to generate Verilog RTL code of the communication unit to study the actual circuit timing and area.