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Develop A Yield Enhancement Framework based on Main Branch Decision Tree Algorithm for Mining Semiconductor Data – An Empirical Study of A DRAM Fab
Thesis

Develop A Yield Enhancement Framework based on Main Branch Decision Tree Algorithm for Mining Semiconductor Data – An Empirical Study of A DRAM Fab

Yen-Chung, Lai
Masters, 國立清華大學, 工業工程與工程管理學系
2004

Abstract

故障排除 良率提昇 決策樹 資料挖礦 類別不平衡 半導體製程 主幹式決策樹法則 trouble shooting yield enhancement decision tree data mining class imbalanced problem semiconductor manufacturing main branch decision tree algorithm
In order to response the production promoting, cost-reducing and quality-improving in semiconductor industry, engineers need effective analytical method to deal with relevant data analysis and decision problem. While making trouble shooting in semiconductor industry, engineers can not only use the expert knowledge on physics or electronics to answer the problem because of numerous relevant analysis factors. At present, only few researchers study how to acquire knowledge from manufacturing data and describe the characteristic of production system in the form of decision rules. There are almost none related research which is about yield enhancement in semiconductor manufacturing talk about the class imbalanced problem encountered in data analysis. So, this thesis develops a new decision tree algorithm called “Main Branch Decision Tree Algorithm” which is different from the general decision tree. The proposed algorithm concerns about the user-defined focus class in dataset for the specific situation, such as finding the root cause of yield-loss wafer in tremendous instances. And we suggested a framework based on our proposed decision tree algorithm and conducted an empirical study in a DRAM FAB for yield enhancement for validation. We combine the domain expert's experience and data mining methodology to sum up the assignable root-cause of the manufacture system, and offer the engineers the reference basis of solving the problem. We help engineers to shrink the range of possible causes, and shorten the time of trouble shooting, so as to improve yield and prevent more suffered wafer.

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