Abstract
We propose an H.264/AVC main profile encoder based on our in-house IP-level and system-level degign methodology targeted towards a multimedia SOC platform. We employ a flexible four-stage pipelined architecture to enhance the performance. We use a modified mode decision cost formula which can achieve almost the same video quality as that of the reference software. We use multiple memory fetch units to access external memory. For inter prediction, we employ a memory reuse mechanism to reduce memory traffic. We also use direct connection between certain IP to boost the performance. After implementation, our design can real-time encode the video of 352x288 pixels with 30 fps into an H.264 main profile video stream on our platform. With the proposed special mechanisms, our design only needs to run at 18 MHz and can be burned into a 6M gate count FPGA. Comparing with the performance of the reference software, our is 300 times faster with only a little video quality tradeoff.