Abstract
In this paper, a high-speed low-power ROM compiler is developed. In conventional low power ROM design, Selective Bit-Line Pre-charge is the most popular technique used to reduce dynamic power consumption. But most of them don’t refer to its superior advantages on leakage current reduction. In this paper, the leakage current reduction by this technique is investigated in circuits fabricated by technologies that suffer severe off-state leakage issues. Besides, a new operational scheme to improve its accessing speed is proposed, which allows word line signal to overlap with pre-charge signal. According to simulation results, the new operational scheme leads to 20% enhancement in accessing speed, at the cost of 2% increase in dynamic power. This high-speed low-power ROM architecture is implemented by using Memory Compiler. It can support 3 kinds of Mux configurations for area / speed optimization. This ROM compiler can generate 109616 kinds of ROM instances. Instances size range from 1024 to 2M bits. A test chip covers all necessary instances by 90nm CMOS low power technology is fabricated. Testing results show that the access time of 8192x32m16 (256Kb) ROM instance is 3.0 ns, which is comparable to SRAM performance. Standby current is 11.41µA at 1.2V/25°C; dynamic operation current is 2.65mA at 1.2V/25°C/100MHz. The new scheme allows for 10X standby current reduction and 5X active power reduction