Abstract
Among many types of CMOS ADC architectures, a pipelined architecture can achieve high input frequency dynamic performances and as a high throughput as the flash ADC due to a Sample and Hold (S/H) circuit in each stage for concurrent processing. CMOS process is making the transition from 0.35µm, and 0.18µm to 0.13µm. Digital circuits can reduce the power supply voltage as the process advances, but for analog circuits, however, it is a great challenge to design the low voltage circuits for a circuit designer. As far, the power supply of the ADC is from 1.5V to 3.3V, because the gain and margin of opamp is difficult to design. This research focuses on high speed, high resolution pipelined analog to digital converters, and self-calibration at last stage, which are needed in applications such as medical imaging, high performance video, high data rate digital radio receivers, and in some telecommunications systems. Here, this thesis describes the design of a 10-bit 50MHz pipeline ADC implemented by simulation with 0.35um (2P4M) process. The ADC consists of eight 1.5-bit stages and final stage is a 2-bit stage. It consists of full differential S/H, which is mainly intended for front-end use in high speed ADC. At ADC last stage, we calibrate the error of comparator offset to prevent the non-monotonicity.