Abstract
We present a divide-and-conquer methodology for SRAM yield analysis. The ultimate goal is to accelerate the speed of yield analysis without missing accuracy. There are two major techniques in this methodology. Firstly, we attempt to establish the model of control circuit output signal through HSPICE simulation. Secondly, we use the model from first step to re-generate input pattern waveforms for 8×8 SRAM array. Then, take these waveforms into 8×8 SRAM array HSPICE file and run simulation. Finally, we can get a yield prediction value. Experimental results shows that this two-level abstraction method can speed up the yield estimation process by 300 times, whereas keeping the estimation error to only 3% as compared to the traditional time-consuming simulation with the entire SRAM circuit.