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Dynamic Data Migration to Eliminate Bank-level Interference for Stencil Applications in Multicore Systems
Thesis

Dynamic Data Migration to Eliminate Bank-level Interference for Stencil Applications in Multicore Systems

Chen, Yen-Hao
Masters, 國立清華大學, 資訊工程學系
2013

Abstract

動態排程 模板應用程式 記憶庫衝突 記憶體干擾 dynamic scheduling stencils bank conflicts memory interference
A stencil computation repeatedly updates each point of a d-dimensional grid as a func-tion of itself and its near neighbors. Modern automatic transformation compiler framework can generate ecient tiling parallel stencil codes. Dynamically scheduling parallel stencils signi cantly improves system performance. However, memory contention problem exacer-bates because of less idling cores and more memory requests sent to the DRAM memory in the same period of time. Traditional OS page coloring method which partitions the memory pages in advance can not alleviate the memory contention in dynamic scheduling parallel stencils. To address this issue, we provide a new software/hardware cooperation dynamic data migration method. Experimental evaluation in a 8-core x86 system shows that our method can improve the system performance by 7% as compared with dynamic scheduling stencils in 8-cores 4-memory banks system and by 9.3% in 16-cores 4 memory banks system.

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