Abstract
Previously, a fast and accurate static NoC timing simulator was proposed to calculate packet-arrival times. It can support different models of worm-hole switching, Global Asynchronous Local Synchronous (GALS) schemes, and Dynamic Voltage and Frequency Scaling (DVFS). However, the NoC simulator is limited to static simulation, i.e., packet injection times were known before simulation starts. Besides, the simulation time grows more than linearly as the number of injected packets increases, because the implementation scan all previous packets to make sure later packets do not interfere previous calculations. In this thesis, we first adapt the NoC timing simulator to support dynamic simulation, which use a windowing technique to detect and recovery the timing errors caused by newly-injected packets. In the mean time, we improve the performance of simulation significantly under large workloads. Also, we extend our NoC timing simulator to support most of the important NoC design parameters, including router pipeline architectures and several arbitration policies. Lastly, we wrap the simulator with SystemC TLM-2.0 (IEEE 1666) sockets for modeling compatibility with other IPs. The results of the proposed simulator are verified with NoC implementations (cycle-accurate RTL-level) created by a NoC compiler from Arteris. All timing results match perfectly with packet waveforms generated by above NoCs. We also achieve significant speed up when comparing with existing NoC simulators. As a reference, the simulator is about 2 times faster than a TG2 NoC model, which is a SystemC and cycle-based model without timing accuracy (due to worm-hole traffics). For other accurate models, the proposed dynamic simulator is 4 times faster than the static version, and about 188 times faster than a Arteris cycle-accurate model.