Abstract
With the rapid evolution of technology, IR-drop has become a major concern in current VLSI designs. An insufficient construction of power distribution network (PDN) leads to severe voltage (IR) drop, because of localized logic cells switching and the PDN may not be enough to support the current demand in the IR-drop hot spot. This problem may affect the performance of the chip seriously. In a conventional integrated circuit (IC) design flow, once a post-route design violates the IR-drop constraint, the design is usually discarded, we should redesign the PDN by iterating back to earlier stages, because traditional repair methods, such as power stripe widening and insertion, are unlikely to succeed due to routing congestion in post-route stage. It may take extra unpredictable turnaround time. In order to avoid the great costs of redesigning the chip, an engineering change order (ECO) approach to mitigate the IR-drop at the post-route stage by the commercial automatic P&R tool, is preferred. In this work, the gradient descent algorithm is used to select the regions that require reinforcement by using ECO power wires that have a detour-shape. We utilize the remaining white space to enhance the PDN. The experimental results on a test set of ITC'99 benchmark circuits show that, in the post-route stage, the worst-case dynamic IR-drop can be mitigated by our ECO approach from 15.50% to 8.79%. That is to say, the improvements of dynamic IR-drop is 43.29%.