Abstract
Because the advantage of DRAM is its structural simplicity: high densities and more inexpensive than other type of RAM, it is very suited to be a role of main-memory in computer architecture. However, for many years, DRAM access latencies have not decreased at the same rate as microprocessor cycle times. In other words, the rate of improvement in processor speed exceeds the rate of improvement in DRAM memory speed, that W. Wulf and S. McKee called the phenomenon "memory wall". Therefore, in past few decades, people do not blindly upgrades single processor’s performance, but increasing the amount of on-chip cores or using the NoC-based many-core architecture for the throughput and low power consumption. Unfortunately, the demand for memory bandwidth or throughput is still increased. Therefore, many engineers dedicate to improve the efficiency between memory controller and DRAM by proposing better memory scheduling policy, increasing bandwidth and improving the access speed, etc. Recently, the emergence of 3D-stacked DRAM (wide I/O) slightly reduces the speed gap between processor and memory system. But the many-core architecture which use mesh or torus architecture a bridge to connect processors and memory controllers has a characteristic that some DRAM request from processor may go through very far distance to access memory controller. Based on the above motivation, we present an architecture which improves the efficiency of accessing stacked memories and reduce routing time on many-core platform. We use an extra crossbar switch interconnect to transport the DRAM request and groups few numbers of processor to specify DRAM-channel. We call the traditional method as \textbf{Original approach} and call our proposed architecture as \textbf{CS-based approach}. Experimental results of SPLASH2 applications demonstrates speed up that ranges from 1.02 to 1.13 times, with crossbar switch interconnect.