Abstract
In modern semiconductor industry, it keeps following Moore’s law. Short channel effects (SCE) has always been a serious issue to familiar with. As a result of this, CMOS device turned form traditional two-dimensional (2D) structure into a three-dimensional (3D) structure, which is well known as FinFETs. This study, we describe some strategies to design CMOS devices by tuning FinFET structure to gain better electrical properties with same doping concentration. The structure parameters including spacer length (LSP), Top Fin-Width (FWT), Bottom Fin-Width(FWB) and Fin-Height (FH). The simulation result shows that LSP will largely affect device electrical properties, and it will be different as gate length (LG) changing. The LSP should be design to fit the requirement. To simplify the mission, this research focuses on a fixed LSP condition and varies other structure parameters. It is well known that, increasing FH can effectively gain saturation current(ISAT). A 1 nm increment of FH approximately can gain additional 2% current. One of its advantages is that it would not affect threshold voltage (VTH) a lot. But a higher FH means that a larger aspect ratio, thus a harder manufacturing process. Increasing FWB to gain current may not be a good choice due to its inefficient. It can only gain additional 1% current. Even a wider FWB lets a larger cross section for epitaxy source and drain, but it also increases device area, which contradicts the requirement of modern semiconductor industry. Tuning FWT may be the best choice to have a current gain. Additional 1 nm FWT can gain extra 4% current, which is the highest in these three options. Moreover, it would not influence VTH a lot, and it is good for source drain epitaxy. In conclusion, this study suggests some options to gain current. We also analyze how these strategies influence electrical properties. Finally, we conclude that FinFET can continue Moore’s till 5 nm technology node.