Abstract
Many researches have shown that critical paths are rarely activated. The concept of rarely activated cannot be characterized by a static timing analysis. In this thesis, we propose a new timing analysis method called Timed Cumulative Probability Density Function (Timed-CDF). Timed-CDF is a probability distribution of a circuit’s stable time induced by input patterns. We present an efficient way for constructing the Timed-CDF. We formulate input patterns inducing outputs to satisfy a certain time constraint as a Boolean function called Timed Characteristic Function (TCF). After constructing a TCF of a time constraint, an efficient functional simulation will be used to find input patterns, which are used to plot the Timed-CDF. Furthermore, we propose a time constraint selecting method to find more accurate Timed-CDF. A legal input patterns generator is also presented for sequential circuits. On average, our experimental results can be 6.18 faster than Verilog simulation for MCNC combinational benchmarks, and in some cases, up to 16 times faster.