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Efficient VLSI Architectures for Inter and Intra Mode Decision in High Resolution H.264/MPEG-4 Part10 AVC Encoding
Thesis

Efficient VLSI Architectures for Inter and Intra Mode Decision in High Resolution H.264/MPEG-4 Part10 AVC Encoding

Huang-Chih Kuo
Masters, 國立清華大學, 資訊工程學系
2005

Abstract

H.264先進影像壓縮技術 幅內模式選擇器 幅間模式選擇器
We propose two efficient hardware architectures for inter and intra mode decision, respectively, in high resolution H.264/AVC encoding. Our approach delivers almost the same video quality as the H.264/AVC reference software does. Our inter mode decision architecture employs a novel resource sharing scheme to support multiple reference frames. Synthesized using a TSMC .13μm CMOS cell library, our inter mode decision unit and intra mode decision unit take 28k and 25k gates, respectively, for 100 MHz performance. Both units can encode 720p HD (1280x720) video at 30 frames per second when running at a 25-MHz FPGA platform. We have integrated the proposed mode decision units into an H.264/AVC main profile encoder system using a multimedia SOC platform.

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