Abstract
Software pipelining is a powerful loop optimization technologyi in compiler. It overlaps the execution of adjacent loop iterations to improve performance. However it has to consider many constraints in the scheduling phase to achieve this purpose. Many miscellaneous algorithms of software pipelining have already come out and we propose a method for a clustered VLIW DSP processor known as PAC platform. We enable the work of the software pipelining with ORC over PAC platform. However, ORC is not available for the PAC platform. The ORC is originally construct for IA-64 architectures. We need to modify ORC to fit PAC architectures. There are mainly three differences between PAC and IA-64 architectures. First, The VLIW data paths of PAC architectures are clustered. We have to assign instructions to appropriate clusters and deal with communications between clusters. Second, there is no rotating register hardware support in PAC architectures. The code generations of ORC must be modified, otherwise it may cause errors. We reference previous work called modulo variable expansion to solve the problem. Third, there are ping-pong constraints when we access the global register files of PAC architectures. We use our data structures to consider this constraint and we modify the modulo scheduling of software pipelining. We run the experiment by Instruction Set Simulator for PAC DSP architecture and we take DSPstone suite as our benchmark. We compare the results of different optimization levels and different number of clusters of software pipelining. The result shows that there is at least 2 times speedup for each case of ii the benchmark by incorporting our scheme over -O0 code generations.